Semiconductor Design Enablement - Testsite Coordinator

We are seeking a test chip design enablement engineer who can work in a highly multi-disciplinary, multi-cultural environment to work on Semiconductor and or Quantum applications at IBM Research. This candidate will be leading and supporting IBM research and development activities in semiconductor and/or superconducting circuit technology, focusing on test chip enablement and hardware program management. This role will be responsible for multiple aspects of our IBM Research’s design & tapeout activities including test chip technical coordination and planning, In this role the individual will define and manage test chip execution milestones from design conception to final test. In addition, this role may include additional design enablement components including development & execution of data processing scripts and algorithms, tape-out operations and logistics, design services automated fill and post-design retargeting data manipulation, and kerf/scribe development. Drive end-to-end tech chip development and tape out activities, including project scope definition, development of schedule/milestones, identification of critical dependencies, progress tracking, issue resolution and communication of status & priorities. Collaborate across a broad team (technology development, process integration, patterning, metrology, design & enablement teams) to deliver test chps to meet technology development and customer requirements. Review design data at multiple stages of test chip development including prior to submission for reticle manufacturing. Manage change control for design updates and reticle ordering. Coordinate design & waiver reviews to disposition design errors which may result in defects in the fabrication line. Support data preparation and mask release activities including handling of design data manipulation steps or scripts. Develop scripts and/or Python code to support test chip development flow and design data manipulations. Identify and drive opportunities for operational and quality improvements Bachelor or above Degree in Electrical Engineering, Computer Engineering, Physics Engineering or related field with experience in VLSI chip development or semiconductor technology Basic understanding of physical layout, technology ground rules, and semiconductor processing.

Preferred technical and professional experience

• Familiarity with layout verification tools from Cadence Pegasus, Synopsys ICV< or Siemens Calibre, including design rule checking (DRC) with 2 years of relevant experience. Strong understanding of Linux environments and shell scripting with a minimum of 2 years experience. Ability to independently troubleshoot and solve complex problems. Strong communication and interpersonal skills. Ability to work collaboratively and effectively within a team.
• Experience with Program Management. Experience with semiconductor technology test chip development and mask preparation activities. Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g. GitHub, Bitbucket) Experienced user of Synopsys ICV DRC checking tool. Experience with advanced sub-micron semiconductor technology nodes. Experience with Python or other scripting/programming language (i.e. Perl), at least 2 years. United States Infrastructure & Technology Professional Albany, US