Senior Silicon Physical Design STA Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and drive to the implementation of physical design Static Timing Analysis (STA) methodologies.
• Take ownership of STA of one or more physical design partitions and top level.
• Drive to the closure of timing and power consumption of the design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design STA constraints rule sets for the physical design engineers.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
• 5 years of experience with Static Timing Analysis (STA) convergence on blocks, Subsystem (SS) or SoC.
• Experience with System on a Chip (SoC) cycles.
• Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

• Master’s degree in Electrical Engineering.
• Experience in coding with System Verilog and scripting with Tool Command Language (TCL).
• Experience in Very-Large-Scale Integration (VLSI) design in SoC or experience with multiple-cycles of SoC in ASIC design.
• Experience in coding constraints and scripting with TCL.