Senior Silicon Design Verification Engineer, YouTube Video Accelerators

The Google Deal and Spend Governance Team helps Google to manage commercial agreement and spend governance and the universe of risks associated with these commitments.Working closely with partners and leadership across Google's Controllership, Finance, Sales, Product, Legal, and Marketing teams, you will ensure that the policies and processes used for Google's commitments to external partners are effective and efficient, that riskiest and most costly commitments have executive cross-functional leadership support, and that Google is managing risk smartly across the business. In doing so, you will regularly engage Google’s most executive leadership to ensure they have the visibility and information needed to make good decisions. At the same time, you will maintain close connections with global teammates working to keep Google’s overall control environment strong. The name Google came from "googol," a mathematical term for the number 1 followed by 100 zeros. And nobody at Google loves big numbers like the Finance team when providing in depth analysis on all manner of strategic decisions across Google products. From developing forward-thinking analysis to generating management reports to scaling our automated financial processes, the Finance organization is an important partner and advisor to the business.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $128000 - $187000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google. Responsibilities

• Lead comprehensive verification strategies and signoff for complex blocks where the source is C/C++, taking full ownership of quality from HLS code to generated RTL.

• Design and maintain advanced environments, including C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and system interactions.

• Employ HLS-specific methods such as C/RTL co-simulation, formal equivalence verification, and transaction-level modeling to ensure hardware fidelity.

• Drive complex bug hunting and coverage analysis across both C++ and RTL domains to ensure complete verification of the design transformation.

• Partner with design teams to optimize C++ code for verifiability and mentor junior engineers on the nuances of HLS verification.

Qualifications Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with Design Verification.

• Experience with SystemVerilog and Universal Verification Methodology (UVM).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Practical experience with High-Level Synthesis tools (e.g., Catapult, Vivado, XLS) and strong C/C++ skills for developing HLS testbenches and models.

• Expertise in video processing, image pipelines, or video compression standards such as AV1, AV2, or H.264.

• Demonstrated ability to debug complex issues across C/C++ and RTL levels using industry-standard EDA tools like VCS, Xcelium, or Verdi.