Sr/ IC Design Engineer (Design Verification)

Job Descriptions

• Develop and Review Test Plan based on IC design specification

• Develop constrained-Random verification environment for complex DUT

• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance

• Implement coverage matrix using cover point and assertion

• Create and debug tests for DUT

• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with 1 year or more experience

• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM

• Strong understanding of verification process from test plan to coverage completion

• Strong communication and Analytical skills

• Understanding of HDL (Verilog, VHDL)

• Experience in using leading EDA software tools like Cadence/ Synopsys

Ethos Search Associates Pte. Ltd.

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