Circuit Design Engineer - Library/Process Monitor

About the Role

Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never envisioned! We have an extraordinary opportunity for Standard Cell Designers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering products to market quickly.

Description

Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will drive concepts of transistor level circuit design, modeling and performance analysis, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new ideas, as well as work with a team of hardworking engineers. As a Circuit Design Engineer for the custom circuits team, you will perform the following:

•\\tWork on library architecture discussion \u0026 optimization effort to improve overall Library PPA.

•\\tDrive layout optimization effort by identifying \u0026 reducing parasitics to push circuit PPA.

•\\tWork on Library PPA for different technology, architecture, PDK releases.

•\\tDevelop standard cell circuits that push design PPA.

•\\tWork on PNR block to design process monitor IP, validate other Ips in testchips

•\\tEngage with CPU, SOC and GPU teams on physical design requirements.

Minimum Qualifications

• BSEE or MSEE with VLSI coursework
• Experience with Digital Circuit Design with Physical Design experience.
• Strong understanding of CMOS device characteristics and design rules.
• Strong understanding of Digital circuits \u0026 optimization for better PPA.
• Good layout design knowledge \u0026 parasitic optimization in various types of layouts.
• Hands-on experience running SPICE simulations and high sigma variation analysis.
• Strong proficiency in scripting languages like Perl, Python, and Tcl.
• Great teammate with good communication and analytical skills.

Preferred Qualifications

• Experience in Circuit design of high-performance flip flops, level shifters, retention flops and other complex circuits is a plus.
• Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) is a strong plus.
• Knowledge of deep submicron process issues \u0026 Finfet Technologies is a plus.
• Understanding of Timing characterization \u0026 modeling of Standard cell circuits is a plus.