SoC Design Verification Engineer

About the Role

Do you have a passion for invention and self-challenge? This position gives you the opportunity to be a part of one of the most innovative and key projects that Apple’s Silicon Engineering Group has embarked upon to date.

As part of our team, you will have the opportunity to take the lead and contribute to verifying a set of sophisticated SoCs that are driving Apple’s flagship Cellular 5G platform. As a member of this team you will integrate multiple sophisticated IP-level DV environments, craft highly reusable UVM TB, implement effective coverage-driven and advised test infrastructure, deploy new tools, develop and deploy AIML methodology, and implement ideas to improve the quality of tape-out readiness of all our chips.

By collaborating with other product development groups across Apple, you can push the industry boundaries of what complex SoCs can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a large-scale SoC, different types of SoC architecture, many high-speed layered protocols, the industry’s standard methodologies on low-power architecture, outstanding DV methodology, verification on accelerated platforms, knowledge of cellular protocol, FW-HW interactions, complexities of multi-chip SoC debug architecture, etc.

Description

As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs! This position requires someone comfortable with all areas of SoC design verification engineering. We are looking for someone who thrives in a dynamic multi-functional organization, is not afraid to debate ideas openly, and is flexible enough to shift within constantly evolving requirements.

Minimum Qualifications

• Bachelors degree required
• Demonstrated knowledge of object-oriented programming principles through coursework, research, or project experience in any OOP-based language (e.g., Python, C++, Java, or SystemVerilog).
• Coursework in Digital Design.

Preferred Qualifications

• MSEE, MSCS or beyond is preferred.
• Coursework in Computer Architecture, Networking Protocol.
• Hands-on experience developing UVM-based testbenches in SystemVerilog, demonstrating applied understanding of object-oriented programming.
• Experience in Digital Design.
• Experience in Developing Reference Model of DUT and Verification using HVL.
• Excellent communication, problem-solving skills, and the desire to seek diverse challenges.